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GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
June 1997 Revised December 2000
GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on the A port eliminates the need for external pull-up resistors on unused inputs. s Power up/down and power off high impedance for live insertion s 5 V tolerant inputs and outputs on the LVTTL ports s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -32 mA/+32 mA s GTLP Buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number GTLP16616MEA GTLP16616MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS500017
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GTLP16616
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA A1-A17 B1-B17 Description A-to-B Output Enable (Active LOW) B-to-A Output Enable (Active LOW) A-to-B Clock Enable (Active LOW) B-to-A Clock Enable (Active LOW) A-to-B Latch Enable (Transparent HIGH) B-to-A Latch Enable (Transparent HIGH) GTLP Reference Voltage A-to-B Clock B-to-A Clock A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs CLKIN CLKOUT B-to-A Buffered Clock Output GTLP Buffered Clock Output of CLKAB
Connection Diagram
Functional Description
The GTLP16616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control both the 17 bits of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1) Inputs CEAB X L L X X L L H OEAB H L L L L L L L LEAB X L L H H L L L CLKAB X H L X X A X X X L H L H X Output B Z B0 (Note 2) B0 (Note 3) L H L H B0 (Note 3) Clocked storage of A data Clock inhibit Mode
Latched storage of A data Transparent

X
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH prior to LEAB going LOW. Note 3: Output level before the indicated steady-state input conditions were established.
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GTLP16616
Logic Diagram
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GTLP16616
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC ESD Rating Storage Temperature (TSTG) 80 mA 64 mA
-0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V
Recommended Operating Conditions (Note 6)
Supply Voltage VCC VCC VCCQ Bus Termination Voltage (VTT) GTLP Input Voltage (VI) on A Port and Control Pins HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) 0.0V to 5.5V 3.15V to 3.45V 4.75V to 5.25V 1.35V to 1.65V
-64 mA
-32 mA +32 mA +34 mA -40C to +85C
-50 mA -50 mA +50 mA >2000V -65C to +150C
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VIK VOH A Port B Port Others B Port Others GTLP GTL VCC = 3.15V, VCCQ = 4.75V VCC, VCCQ = Min to Max (Note 8) VCC = 3.15V VCCQ = 4.75V VOL A Port VCC, VCCQ = Min to Max (Note 8) VCC = 3.15V VCCQ = 4.75V B Port II Control Pins A Port VCC = 3.15V VCCQ = 4.75V VCC, VCCQ = 0 or Max VCC = 3.45V VCCQ = 5.25V B Port IOFF II(hold) IOZH IOZL VCC = 3.45V VCCQ = 5.25V A Port and Control Pins VCC = VCCQ = 0 A Port A Port B Port A Port B Port VCC = 3.15V, VCCQ = 4.75V VCC = 3.45V, VCCQ = 5.25V VCC = 3.45V, VCCQ = 5.25V IOL = 34 mA VI = 5.5V or 0V VI = 5.5V VI = VCC VI = 0 VI = VCC VI = 0 VI or VO = 0 to 4.5V VI = 0.8V VI = 2.0V VO = 3.45V VO = 1.5V VO = 0 VO = 0.65V 75 -20 1 5 -20 -10 0.65 10 20 1 -30 5 -5 100 A A A A A A V A IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 32 mA VCC -0.2 2.4 2.0 0.2 0.5 V V II = -18 mA 1.0 0.8 -1.2 Test Conditions Min VREF +0.1 2.0 0.0 VREF -0.1 0.8 Typ (Note 7) VTT Max Units V V V V V V V
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GTLP16616
DC Electrical Characteristics
Symbol ICCQ (VCCQ) A or B Ports VCC = 3.45V, VCCQ = 5.25V, IO = 0, VI = VCCQ or GND ICC (VCC) ICC (Note 9) A or B Ports VI = VCC or GND A Port and Control Pins VCC = 3.45V, VCC = 5.25V, A or Control Inputs at VCC or GND CIN CI/O CI/O Control Pins A Port B Port
(Continued)
Min Typ (Note 7) 30 30 30 0 0 0 0 40 40 40 1 1 1 1 mA mA mA Max
Test Conditions Outputs HIGH Outputs LOW Outputs Disabled Outputs HIGH Outputs LOW Outputs Disabled One Input at 2.7V
Units
VCC = 3.45V, VCCQ = 5.25V, IO = 0,
VI = VCCQ or 0 VI = VCCQ or 0 VI = VCCQ or 0
8 9 6 pF
Note 7: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25C. Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX tW Maximum Clock Frequency Pulse Duration LEAB or LEBA HIGH CLKAB or CLKBA HIGH or LOW tS Setup Time A before CLKAB B before CLKBA A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA tH Hold Time A after CLKAB B after CLKBA A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA Min 175 3.0 ns 3.2 0.5 3.1 1.3 3.7 0.7 1.0 1.5 0.0 0.5 0.0 1.5 1.7 ns ns Max Unit MHz
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GTLP16616
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol From (Input) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tSKEW tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ
Note 10: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25C. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for the CLKOUT pin and any B output transition when measured with reference to CLKAB. This guarantees the relationship between B output data and CLKOUT such that data is coincident or ahead of CLKOUT. This specification is guaranteed but not tested.
To (Output) B
Min
Typ (Note 10)
Max
Unit
A
1.0 1.0
4.3 5.0 4.5 5.3 4.6 5.4 6.2 5.7 4.4 6.1
6.5 ns 8.2 6.7 ns 8.7 6.7 ns 8.7 10.0 ns 10.0 6.3 ns 9.8 2 ns ns
LEAB
B
1.8 1.5
CLKAB
B
1.8 1.5
CLKAB
CLKOUT
3.0 3.0
OEAB
B or CLKOUT
1.6 1.3
B (Note 11)
CLKOUT
0 2.6 2.6 2.0 1.4 5.6 5.0 4.2 3.3 4.4 3.5 6.0 6.4 5.0 3.9
Transition time, B outputs (20% to 80%) Transition time, B outputs (20% to 80%) B A
8.2 ns 7.2 6.3 ns 5.0 6.8 ns 5.2 10.0 ns 10.0 6.4 ns 8.0
LEBA
A
2.1 1.9
CLKBA
A
2.3 2.1
CLKOUT
CLKIN
3.0 3.0
OEBA
A or CLKIN
1.5 1.4
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GTLP16616
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
CL includes probes and jig capacitance. CL includes probes and jig capacitance. For B Port outputs, CL = 30 pF is used for worst case edge rate. Voltage Waveforms Pulse Duration (Vm = 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay and Setup and Hold Times (Vm = 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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GTLP16616
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300" Wide Package Number MS56A
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GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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